1. Field of the Invention
This invention relates generally to a method for determining the depth of an etching procedure and, more particularly, to a method for determining the depth of etching in a semiconductor device by determining the kink current in the source-drain, current-voltage relationship.
2. Discussion of the Prior Art
Three terminal field effect transistors are well known and are useful element in many electronic circuits, where a gate electrode is used to control the current flow between the source and drain regions. As shown in FIG. 1, such a device 10 includes a substrate 12, a source region 14, a drain 16, a channel layer 18 extending between the source and drain, a Schottky barrier layer 20 and a cap layer 22. The gate electrode 24 is preferably placed in direct contact with the Schottky barrier layer. Thus, it is necessary to etch the cap layer and place the gate electrode within a recess 26. By doing this, the source resistance is kept low and the frequency performance of the device is increased. However, the recess depth must be carefully determined to optimize device performance.
Prior art GaAs and InP based FETs measured the saturation current, 32, of the source-drain (S-D), current-voltage (I-V) relationship in order to determine the recess etch depth. After each etching cycle, the I-V curve is remeasured to determine the change in the saturation current, 32. As seen in FIG. 3, as the etching time increases on an InP based FET, the saturation current, 32 (shown as square points) decreases. When this current decreases to a predetermined value, the desired etch depth has been reached. However, the saturation current does not decrease strongly with respect to etch time, so a very careful measurement must be made in order to determine the etch depth. Since the gate electrode is formed using the same mask as the recess etch, the I-V measurement must be taken through a photoresist layer. Small changes in I-V current are difficult to measure since contact must be made through the photoresist layer.
Accordingly, one object of the present invention is to provide a method for etching a gate recess for an InP based FET device.
Another object of this invention is to control the etch depth in an InP based FET device by referencing the kink current in the source to drain I-V relationship.
Another object of this invention is to provide a method for forming an InP based FET device wherein a gate electrode is placed in a recess, the depth of which is determined by the kink current of the source-drain, current-voltage relationship.
A further object of this invention is to use a measured kink current to determine the time of etching of an InP based FET device.
Briefly, these and other objects of the invention are achieved by providing a measurement of the source-drain current voltage relationship before etching the device. After each cycle of etching, the relationship is again examined. The kink current is then examined and the etching time determined based on this kink current.